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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
26 lines
541 B
Verilog
26 lines
541 B
Verilog
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/*
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* Generate a barrel shifter of arbitrary width.
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* T can be 0 for <<, 1 for >>, 2 for <<< or 3 for >>>.
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*/
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module shift
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#(parameter WI = 4, WS = 4, parameter WO = 6)
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(input wire [WI-1:0] D,
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input wire [WS-1:0] S,
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output wire [WO-1:0] SHL,
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output wire [WO-1:0] SHR,
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output wire signed [WO-1:0] ASHL,
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output wire signed [WO-1:0] ASHR
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/* */);
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wire signed [WI-1:0] DS;
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assign DS = D;
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assign SHL = D << S ;
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assign SHR = D >> S ;
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assign ASHL = DS <<< S ;
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assign ASHR = DS >>> S ;
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endmodule
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