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Lars-Peter Clausen
5ef847ea87
SystemVerilog supports type parameters. These are similar to value parameters, but they allow to pass a type to a module or similar when instantiating it. E.g. ``` module A #(parameter type T = int); endmodule module B; A #(.T(real)) i_a; endmodule ``` Add support for handling type parameters. For the vlog95 and vhdl backends type parameters, similar to typedefs, get replaced with their actual value. For modules with non-local type parameters for each module instance a unique module or architecture is generated with the actual type. Querying type parameters through VPI is not yet supported. Signed-off-by: Lars-Peter Clausen <[email protected]>
THE VVP TARGET SYMBOL NAME CONVENTIONS There are some naming conventions that the vvp target uses for generating symbol names. * wires and regs Nets and variables are named V_<full-name> where <full-name> is the full hierarchical name of the signal. * Logic devices Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In this case the symbol is attached to a functor that is the output of the logic device. GENERAL FUNCTOR WEB STRUCTURE The net of gates, signals and resolvers is formed from the input design. The basic structure is wrapped around the nexus, which is represented by the ivl_nexus_t. Each nexus represents a resolved value. The input of the nexus is fed by a single driver. If the nexus in the design has multiple drivers, the drivers are first fed into a resolver (or a tree of resolvers) to form a single output that is the nexus. The nexus, then, feeds its output to the inputs of other gates, or to the .net objects in the design.