iverilog

History

Cary R 1efa220773 Fix non-blocking assignment to an array error state handling If either the index or part offset expressions generate an undefined value then the assignment is skipped. This patch reworks the code that handles the flags used to detect this. For some simple cases a global flag is not needed, but for other cases one is needed since there are two expressions that can generate an error and even when there is only a variable expression this error state needs to be preserved if there is a variable delay. An undefined delay value defaults to zero and is not an error.		2014-12-09 17:29:18 -08:00
..
Makefile.in	vvp code generator try to generate condition flags directly.	2014-11-19 18:32:19 -08:00
README.txt	tgt-vvp generates code that skips nets as inputs.	2001-08-10 00:40:45 +00:00
cppcheck.sup	Remove some cppcheck warnings	2014-06-28 16:56:09 -07:00
draw_class.c	Allow class properties to be arrayed.	2014-09-15 17:37:30 -07:00
draw_enum.c	updated FSF-address	2012-08-29 10:12:10 -07:00
draw_mux.c	Improbe vvp support for wide mux devices.	2014-07-14 16:46:58 -07:00
draw_net_input.c	Handle some tricky conditions assignments to parts.	2014-07-14 16:46:58 -07:00
draw_substitute.c	Handle some tricky conditions assignments to parts.	2014-07-14 16:46:58 -07:00
draw_switch.c	updated FSF-address	2012-08-29 10:12:10 -07:00
draw_ufunc.c	Remove dead code for allocate_vec handling.	2014-10-24 13:07:53 -07:00
draw_vpi.c	Remove dead stuff_ok_flags from draw_eval_vec4 functions.	2014-10-24 09:32:32 -07:00
eval_bool.c	Remove dead stuff_ok_flags from draw_eval_vec4 functions.	2014-10-24 09:32:32 -07:00
eval_condit.c	Implement %cmp/ne and %cmpi/ne	2014-12-03 11:06:11 -08:00
eval_expr.c	Fix for br962 - pop from dynamic array is not padded to correct width.	2014-11-02 15:26:15 +00:00
eval_object.c	Merge branch 'master' into vec4-stack	2014-12-06 08:24:46 -08:00
eval_real.c	Remove dead stuff_ok_flags from draw_eval_vec4 functions.	2014-10-24 09:32:32 -07:00
eval_string.c	Port %pushv/str to vec4-stack style.	2014-10-24 10:16:35 -07:00
eval_vec4.c	Add the vec4 %subi instruction	2014-12-05 09:45:29 -08:00
modpath.c	updated FSF-address	2012-08-29 10:12:10 -07:00
stmt_assign.c	Fix a %vpi_call call syntax.	2014-12-02 15:28:22 -08:00
vector.c	Remove dead code for allocate_vec handling.	2014-10-24 13:07:53 -07:00
vvp-s.conf.in	Remove redundant back-end selections.	2008-09-07 16:43:54 -07:00
vvp.c	Expression cast handles size if need be.	2014-12-02 16:54:32 -08:00
vvp.conf.in	Remove redundant back-end selections.	2008-09-07 16:43:54 -07:00
vvp_config.h.in	Update header files to use a more standard name to prevent rereading	2014-07-23 13:42:56 -07:00
vvp_priv.h	Expression cast handles size if need be.	2014-12-02 16:54:32 -08:00
vvp_process.c	Fix non-blocking assignment to an array error state handling	2014-12-09 17:29:18 -08:00
vvp_scope.c	Handle arrays of class objects.	2014-08-30 10:18:57 -07:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.


GENERAL FUNCTOR WEB STRUCTURE

The net of gates, signals and resolvers is formed from the input
design. The basic structure is wrapped around the nexus, which is
represented by the ivl_nexus_t.

Each nexus represents a resolved value. The input of the nexus is fed
by a single driver. If the nexus in the design has multiple drivers,
the drivers are first fed into a resolver (or a tree of resolvers) to
form a single output that is the nexus.

The nexus, then, feeds its output to the inputs of other gates, or to
the .net objects in the design.