21 lines
548 B
Verilog
21 lines
548 B
Verilog
// Extended VCD ($dumpports): scalar input / output / inout ports.
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module evcd_basic_dut (input wire a, input wire b,
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output wire y, inout wire io);
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assign y = a & b;
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assign io = a ? b : 1'bz;
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endmodule
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module evcd_basic;
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reg a, b;
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wire y, io;
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evcd_basic_dut u (.a(a), .b(b), .y(y), .io(io));
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initial begin
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$dumpports(u, "work/evcd_basic.evcd");
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a = 1'b0; b = 1'b0; #5;
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a = 1'b1; b = 1'b0; #5;
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a = 1'b1; b = 1'b1; #5;
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a = 1'b0; b = 1'b1; #5;
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$finish;
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end
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endmodule
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