57 lines
1.1 KiB
Verilog
57 lines
1.1 KiB
Verilog
// Regression: class dynamic-array property locator methods.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do if ((val) !== (exp)) begin $display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); failed = 1'b1; end while(0)
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class C;
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int d[];
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endclass
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C c;
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int tmp[];
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int r[$];
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initial begin
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c = new;
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tmp = new[9];
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tmp = '{4, 7, 2, 5, 7, 1, 6, 3, 1};
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c.d = tmp;
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r = c.d.find() with (item > 3);
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`check(r.size, 5);
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`check(r[0], 4);
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`check(r[4], 6);
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r = c.d.find_first() with (item > 6);
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`check(r.size, 1);
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`check(r[0], 7);
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r = c.d.find_last_index() with (item < 3);
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`check(r.size, 1);
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`check(r[0], 8);
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r = c.d.unique();
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`check(r.size, 7);
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`check(r[0], 4);
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r = c.d.unique_index();
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`check(r.size, 7);
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`check(r[0], 0);
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r = c.d.min();
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`check(r.size, 2);
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`check(r[0], 1);
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`check(r[1], 1);
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r = c.d.max() with (item < 7);
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`check(r.size, 1);
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`check(r[0], 6);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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