luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/ivtest/ivltests/pr3441576.v

6 lines
96 B
Verilog
Raw Blame History

module top;
reg foo;
always @* foo <= 0;
initial #1 $display("foo is %b", foo);
endmodule
Reference in New Issue View Git Blame Copy Permalink