50 lines
1.2 KiB
Verilog
50 lines
1.2 KiB
Verilog
module top;
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reg pass = 1'b1;
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genvar lp;
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for (lp=1; lp <= 128; lp = lp + 1) begin: loop
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test #(lp) dut();
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end
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initial #1000 if (pass) $display("PASSED");
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endmodule
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module test;
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parameter wid = 62;
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localparam X = {4'b1000, {wid{1'b0}}};
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localparam Y = {1'b1, {wid{1'b0}}};
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reg [wid:0] y = Y;
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reg [wid+3:0] x = X;
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reg [3:0] res;
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initial begin
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#wid; // Wait for the x and y values to get assigned.
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res = X/Y;
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if (res !== 4'b1000) begin
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$display("Failed const. division for %3d, expected 4'b1000, got %b",
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wid, res);
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top.pass = 1'b0;
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end
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res = X/y;
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if (res !== 4'b1000) begin
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$display("Failed const. numerator for %3d, expected 4'b1000, got %b",
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wid, res);
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top.pass = 1'b0;
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end
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res = x/Y;
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if (res !== 4'b1000) begin
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$display("Failed const. denominator for %3d, expected 4'b1000, got %b",
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wid, res);
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top.pass = 1'b0;
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end
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res = x/y;
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if (res !== 4'b1000) begin
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$display("Failed variable division for %3d, expected 4'b1000, got %b",
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wid, res);
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top.pass = 1'b0;
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end
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end
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endmodule
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