23 lines
447 B
Verilog
23 lines
447 B
Verilog
`begin_keywords "1364-2005"
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module top(arg);
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input [31:0] arg;
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wire [31:0] out_0;
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wire [31:0] out_1;
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reg [31:0] var;
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add dut_0 (var, var, out_0);
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add dut_1 (arg, var, out_1);
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endmodule
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module add(in0, in1, out);
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input [31:0] in0;
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input [31:0] in1;
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output reg [31:0] out;
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// This works if you explicitly specify the sensitivity list.
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always @* out = in0 + in1;
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endmodule
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`end_keywords
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