25 lines
502 B
Verilog
25 lines
502 B
Verilog
module main;
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wire [3:0] b = 4'b1111;
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wire [3:0] c = 4'b1111;
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initial begin
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#0; // avoid time-0 race
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$display("%b", ((c & ~(1'b1<<9'h00)) & b)); // s.b. 1110
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$display("%b", |((c & ~(1'b1<<9'h00)) & b)); // s.b. 1
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if ( ((c & ~(1'b1<<9'h00)) & b) !== 4'b1110) begin
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$display("FAILED (1)");
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$finish;
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end
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if (|((c & ~(1'b1<<9'h00)) & b) !== 1'b1) begin
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$display("FAILED (2)");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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