49 lines
842 B
Verilog
49 lines
842 B
Verilog
module top;
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reg pass;
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reg [8:0] a;
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wire [7:0] res_a;
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reg [6:0] b;
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wire [7:0] res_b;
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reg signed [6:0] c;
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wire [7:0] res_c;
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assign res_a = Copy(a);
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assign res_b = Copy(b);
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assign res_c = Copy(c);
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initial begin
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pass = 1'b1;
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a = 9'h101;
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b = -7'd1;
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c = -7'd1;
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#1;
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if (res_a !== 8'h01) begin
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$display("Failed to crop a vector, got %b.", res_a);
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pass = 1'b0;
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end
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if (res_b !== 8'h7f) begin
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$display("Failed to zero extend an unsigned vector, got %b.", res_b);
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pass = 1'b0;
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end
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if (res_c !== 8'hff) begin
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$display("Failed to sign extend a signed vector, got %b.", res_c);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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function [7:0] Copy;
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input [7:0] Value;
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begin
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Copy = Value;
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end
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endfunction
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endmodule
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