103 lines
2.5 KiB
Verilog
103 lines
2.5 KiB
Verilog
// NOTE: This test program is WRONG, in that it ignores the fact
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// that continuous assigns drive with their own strength and drop
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// any strength that the r-value may have.
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module strength();
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wire sup1; assign (supply0, supply1) sup1 = 1'b1;
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wire str1; assign (strong0, strong1) str1 = 1'b1;
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wire pl1; assign (pull0, pull1) pl1 = 1'b1;
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wire we1; assign (weak0, weak1) we1 = 1'b1;
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wire sup0; assign (supply0, supply1) sup0 = 1'b0;
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wire str0; assign (strong0, strong1) str0 = 1'b0;
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wire pl0; assign (pull0, pull1) pl0 = 1'b0;
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wire we0; assign (weak0, weak1) we0 = 1'b0;
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wire sup1_sup0;
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wire sup1_str0;
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wire sup1_pl0;
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wire sup1_we0;
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assign sup1_sup0 = sup1;
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assign sup1_sup0 = sup0;
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assign sup1_str0 = sup1;
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assign sup1_str0 = str0;
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assign sup1_pl0 = sup1;
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assign sup1_pl0 = pl0;
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assign sup1_we0 = sup1;
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assign sup1_we0 = we0;
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initial begin
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#1;
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$display("sup1_sup0 resulted in: %b", sup1_sup0);
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$display("sup1_str0 resulted in: %b", sup1_str0);
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$display("sup1_pl0 resulted in: %b", sup1_pl0);
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$display("sup1_we0 resulted in: %b", sup1_we0);
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end
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wire str1_sup0;
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wire str1_str0;
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wire str1_pl0;
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wire str1_we0;
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assign str1_sup0 = str1;
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assign str1_sup0 = sup0;
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assign str1_str0 = str1;
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assign str1_str0 = str0;
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assign str1_pl0 = str1;
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assign str1_pl0 = pl0;
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assign str1_we0 = str1;
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assign str1_we0 = we0;
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initial begin
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#2;
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$display("str1_sup0 resulted in: %b", str1_sup0);
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$display("str1_str0 resulted in: %b", str1_str0);
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$display("str1_pl0 resulted in: %b", str1_pl0);
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$display("str1_we0 resulted in: %b", str1_we0);
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end
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wire pl1_sup0;
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wire pl1_str0;
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wire pl1_pl0;
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wire pl1_we0;
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assign pl1_sup0 = pl1;
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assign pl1_sup0 = sup0;
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assign pl1_str0 = pl1;
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assign pl1_str0 = str0;
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assign pl1_pl0 = pl1;
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assign pl1_pl0 = pl0;
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assign pl1_we0 = pl1;
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assign pl1_we0 = we0;
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initial begin
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#3;
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$display("pl1_sup0 resulted in: %b", pl1_sup0);
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$display("pl1_str0 resulted in: %b", pl1_str0);
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$display("pl1_pl0 resulted in: %b", pl1_pl0);
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$display("pl1_we0 resulted in: %b", pl1_we0);
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end
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wire we1_sup0;
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wire we1_str0;
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wire we1_pl0;
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wire we1_we0;
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assign we1_sup0 = we1;
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assign we1_sup0 = sup0;
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assign we1_str0 = we1;
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assign we1_str0 = str0;
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assign we1_pl0 = we1;
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assign we1_pl0 = pl0;
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assign we1_we0 = we1;
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assign we1_we0 = we0;
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initial begin
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#4;
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$display("we1_sup0 resulted in: %b", we1_sup0);
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$display("we1_str0 resulted in: %b", we1_str0);
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$display("we1_pl0 resulted in: %b", we1_pl0);
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$display("we1_we0 resulted in: %b", we1_we0);
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end
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endmodule
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