22 lines
431 B
Verilog
22 lines
431 B
Verilog
module test();
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reg clk;
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reg [15:0] usb_shadow [0: 32];
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initial begin
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usb_shadow[6'b0_00000] = 'b0101;
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usb_shadow[6'b1_00000] = 'b1001;
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clk = 0;
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if (usb_shadow[{!clk,5'b0}][15:2] !== 2) begin
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$display("FAILED");
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$finish;
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end
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clk = 1;
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if (usb_shadow[{!clk,5'b0}][15:2] !== 1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // test
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