28 lines
553 B
Verilog
28 lines
553 B
Verilog
`timescale 1us/100ns
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module top;
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reg pass = 1'b1;
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reg [3:0] ia = 4'd1, ib = 4'd2;
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wire signed [3:0] icon;
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assign #1 icon = {ib[1:0], ia[0]}; // Should give 5 after a delay.
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initial begin
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#0.9;
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if (icon !== 4'bx) begin
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pass = 1'b0;
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$display("concatenation value not delayed, expected 4'bx got %b.", icon);
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end
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#0.1;
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#0;
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if (icon !== 4'd5) begin
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pass = 1'b0;
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$display("concatenation value not correct, expected 4'd5 got %d.", icon);
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end
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if (pass) $display("PASSED");
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end
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endmodule
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