47 lines
757 B
Verilog
47 lines
757 B
Verilog
// pr1866215
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module A (CH, CL, SH, SL);
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wire [31:6] S1L;
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wire [39:32] S1H;
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wire [31:6] C1L;
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wire [38:32] C1H;
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output [31:0] SL;
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output [31:0] CL;
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output [47:32] SH;
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output [47:32] CH;
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B B0 (C1H[38:32], {C1L[31:6], CL[5:0]}, S1H[39:32], {S1L[31:6], SL[5:0]});
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initial begin
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#1 $display("C1H=%h, {C1L, CL}={%h, %h}, S1H=%h, {S1L, SL}={%h, %h}",
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C1H, C1L, CL, S1H, S1L, SL);
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end
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endmodule
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module B (CH, CL, SH, SL);
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output [37:32] CH;
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output [31:0] CL;
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output [38:32] SH;
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output [31:0] SL;
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C C0 (CH, CL, SH, SL);
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endmodule
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module C (CH, CL, SH, SL);
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output [38:32] CH;
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output [31:0] CL;
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output [39:32] SH;
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output [31:0] SL;
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assign CH = 6'h33;
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assign CL = 32'h55555555;
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assign SH = 7'h66;
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assign SL = 32'haaaaaaaa;
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endmodule
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