37 lines
512 B
Verilog
37 lines
512 B
Verilog
// Copyright 2007, Martin Whitaker.
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// This code may be freely copied for any purpose.
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module duplicate_names();
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localparam up = 1;
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generate
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if (up)
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begin:block1
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wire [2:0] count1;
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count_up counter(count1);
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end
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endgenerate
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initial begin:block1
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reg [2:0] count2;
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#1 count2 = 4;
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#1 count2 = 5;
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#1 count2 = 6;
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#1 count2 = 7;
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end
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endmodule
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module count_up(output reg [2:0] count);
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initial begin
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#1 count = 0;
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#1 count = 1;
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#1 count = 2;
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#1 count = 3;
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end
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endmodule
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