30 lines
523 B
Verilog
30 lines
523 B
Verilog
module test;
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reg [8:0] t1;
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initial
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main;
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function integer log2;
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input [31:0] arg;
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for (log2=0; arg > 0; log2=log2+1)
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arg = arg >> 1;
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endfunction // log2
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task main;
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integer temp;
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begin
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t1 = 9'h0a5;
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temp = log2($unsigned(t1 - t1 - 1'b1));
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$display("%d", temp);
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temp = log2($signed(t1 - t1 - 1'b1));
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$display("%d", temp);
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temp = log2({t1 - t1 - 1'b1});
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$display("%d", temp);
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temp = $bits(t1 - t1 - 1'b1);
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$display("%d", temp);
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end
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endtask
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endmodule
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