30 lines
386 B
Verilog
30 lines
386 B
Verilog
module adding;
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reg signed [20:0] s3, s4;
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reg signed [21:0] t1, t2;
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reg clk;
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initial begin
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clk=0;
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s3=+400000;
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s4=+200000;
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#10;
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clk=1;
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#10;
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$display("%d %d", t1, t2);
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clk=0;
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s3=-400000;
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s4=-200000;
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#10;
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clk=1;
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#10;
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$display("%d %d", t1, t2);
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$display("%s", (t1==t2) ? "PASSED" : "FAIL");
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end
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always @(posedge clk) begin
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t1 <= s3 + 2*s4;
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t2 <= s3 + s4*2;
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end
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endmodule
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