36 lines
593 B
Verilog
36 lines
593 B
Verilog
// pr1691599b.v
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//
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module main;
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parameter cnt = 4;
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genvar i;
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generate
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for (i = 0; i < cnt; i = i+1) begin : target
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reg [1:0] val;
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end
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endgenerate
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initial begin
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target[0].val = 0;
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target[1].val = 1;
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target[2].val = 2;
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target[3].val = 3;
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end
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generate
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for (i = 0; i < cnt; i = i+1) begin : sink
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wire [1:0] val = target[i].val;
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initial #1
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if (val !== i) begin
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$display("FAILED: sink[%0d].val = %b", i, val);
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$finish;
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end
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end
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endgenerate
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initial #10 $display("PASSED");
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endmodule // main
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