33 lines
539 B
Verilog
33 lines
539 B
Verilog
// pr1664684
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module bug (rdo, rm, cpen, up14, rdi);
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output [31:0] rdo;
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input rm, cpen;
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input [31:0] up14, rdi;
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initial $monitor($time,,rdo,,rm,cpen,,up14,,rdi);
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assign rdo = (rm | cpen) ? up14 : rdi;
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endmodule
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module bench;
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reg [31:0] up14;
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wire [31:0] rdo;
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reg rm, cpen;
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tri0 [31:0] rdi;
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bug u1 (rdo, rm, cpen, up14, rdi);
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initial begin
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rm = 1'bX;
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cpen = 1'b0;
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up14 = 'hX;
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#40;
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up14 = 32'd0;
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rm = 1'b0;
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#40;
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$finish(0);
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end
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endmodule
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