42 lines
825 B
Verilog
42 lines
825 B
Verilog
// -*- Mode: Verilog -*-
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// Filename : cnr_tb.v
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// Description : single row corner bender testbench
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// Author :
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// Created On : Thu Mar 23 16:23:01 2006
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// Last Modified By: $Id: pr1492075.v,v 1.1 2006/06/02 05:01:52 stevewilliams Exp $
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// Last Modified On: .
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// Status : Unknown, Use with caution!
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`timescale 1ns / 10ps
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module cnr_tb ();
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reg clkb;
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reg clocken;
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integer cntb;
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// clock generation clkb
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always @ (posedge clocken)
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begin
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for (cntb=0; cntb<5; cntb=cntb+1)
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begin
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#(10 + -2) clkb = 1;
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#(10 - -2) clkb = 0;
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end
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end
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//
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initial
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begin
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$monitor("clkb=%b at %t", clkb, $time);
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clkb = 1'b0;
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clocken = 0;
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#1 clocken = 1;
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#(10*20) clocken = 0;
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#100;
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$finish(0);
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end
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endmodule // cnr_tb
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