44 lines
716 B
Verilog
44 lines
716 B
Verilog
module test;
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reg [2:0] tmp1;
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integer tmp2;
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real tmp3;
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initial begin
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t1(tmp1, 1);
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if (tmp1 !== 2) begin
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$display("FAILED -- tmp1=%b", tmp1);
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$finish;
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end
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t2(tmp2, 4);
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if (tmp2 !== 6) begin
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$display("FAILED == tmp2=%d", tmp2);
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$finish;
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end
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t3(tmp3, 0.5);
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if (tmp3 != 2.0) begin
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$display("FAILED -- tmp3=%f", tmp3);
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$finish;
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end
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$display("PASSED");
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end
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task t1(output [2:0] o, input [2:0] i);
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begin
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o = i + 1;
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end
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endtask // tt
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task t2(output integer o, input integer i);
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o = i + 2;
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endtask // t2
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task t3(output real o, input real i);
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o = i + 1.5;
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endtask // t3
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endmodule
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