48 lines
797 B
Verilog
48 lines
797 B
Verilog
// test.v program starts here
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// This program is based on iverilog report [ 1367855 ] vvp simulation error
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module test();
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reg [3:0] S;
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mux m( .SEL(S) );
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initial begin
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S=3; #100;
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S=2; #100;
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$display("PASSED");
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$finish;
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end
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endmodule
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module mux(SEL);
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input [3:0] SEL;
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wire [3:0] SEL;
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integer offset;
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always @(SEL) begin
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offset = SEL[3] + SEL[0]*128 + SEL[2:1]*2;
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$display("MUX: SEL=%d offset=%b", SEL, offset);
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case (SEL)
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'bxxxx: begin
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end
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2: if (offset !== 'b00000000000000000000000000000010) begin
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$display("FAILED");
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$finish;
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end
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3: if (offset !== 'b00000000000000000000000010000010) begin
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$display("FAILED");
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$finish;
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end
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default: begin
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$display("FAILED -- SEL=%b", SEL);
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$finish;
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end
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endcase
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end
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endmodule
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