48 lines
1.0 KiB
Verilog
48 lines
1.0 KiB
Verilog
module top;
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parameter pval = 7;
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string sval, strvm, strcm, strvl, strcl;
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real ridx;
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integer in;
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reg cavm, cacm, cavl, cacl;
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reg vvm, vcm, vvl, vcl;
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reg pvm, pcm, pvl, pcl;
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reg svm, scm, svl, scl;
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integer calvm, calcm, calvl, calcl;
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integer vlvm, vlcm, vlvl, vlcl;
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assign cavm = in[ridx:1];
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assign cacm = in[0.5:1];
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assign cavl = in[1:ridx];
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assign cacl = in[1:0.5];
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assign calvm[ridx:1] = 1'b1;
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assign calcm[0.5:1] = 1'b1;
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assign calvl[1:ridx] = 1'b1;
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assign calcl[1:0.5] = 1'b1;
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initial begin
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in = 7;
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ridx = 0.5;
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sval = "ABC";
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vvm = in[ridx:1];
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vcm = in[0.5:1];
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vvl = in[1:ridx];
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vcl = in[1:0.5];
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vlvm[ridx:1] = 1'b1;
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vlcm[0.5:1] = 1'b1;
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vlvl[1:ridx] = 1'b1;
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vlcl[1:0.5] = 1'b1;
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pvm = pval[ridx:1];
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pcm = pval[0.5:1];
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pvl = pval[1:ridx];
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pcl = pval[1:0.5];
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svm = sval[ridx:1];
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scm = sval[0.5:1];
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svl = sval[1:ridx];
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scl = sval[1:0.5];
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strvm[ridx:1] = "a";
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strcm[0.5:1] = "a";
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strvl[1:ridx] = "a";
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strcl[1:0.5] = "a";
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end
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endmodule
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