61 lines
1.6 KiB
Verilog
61 lines
1.6 KiB
Verilog
// Copyright (c) 2015 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test for $ivlh_{rising,falling}_edge VPI functions
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// (mostly used by the VHDL frontend).
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module main;
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reg a, b;
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always @(a or b) begin
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if ($ivlh_rising_edge(a))
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$display("%0t: rising_edge(a)", $time);
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if ($ivlh_falling_edge(a))
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$display("%0t: falling_edge(a)", $time);
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if ($ivlh_rising_edge(b))
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$display("%0t: rising_edge(b)", $time);
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if ($ivlh_falling_edge(b))
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$display("%0t: falling_edge(b)", $time);
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end
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initial begin
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#1 a <= 1;
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#1 b <= 1;
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#1 a <= 0;
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#1 b <= 0;
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#1 a <= 0; // nothing should be detected
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#1 b <= 0;
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#1 a <= 1;
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#1 b <= 1;
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#1 a <= 1; // nothing should be detected
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#1 b <= 1;
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#1 a <= 0;
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#1 b <= 0;
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#1 $finish(0);
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end
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endmodule // main
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