83 lines
1.8 KiB
Verilog
83 lines
1.8 KiB
Verilog
// Copyright C(O) 2004 Burnell G West
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// The following text may be utilized and / or reproduced by anybody for
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// any reason.
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//
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// verr.v
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//
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module verr (clk, vout);
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input clk;
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output vout;
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reg vout;
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real start_edge;
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real end_edge;
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wire trigger_en;
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wire [9:0] v_value;
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initial vout = 1'b0;
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always @( posedge clk)
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begin
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if (trigger_en)
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begin
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start_edge = ( v_value[0] * 1.95)
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+ ( v_value[1] * 3.9 )
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+ ( v_value[2] * 7.8 )
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+ ( v_value[3] * 15.6 )
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+ ( v_value[4] * 31.2 )
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+ ( v_value[5] * 62.5 )
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+ ( v_value[6] * 125 )
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+ ( v_value[7] * 250 )
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+ ( v_value[8] * 0 )
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+ ( v_value[9] * 0 )
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+ 0;
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end_edge = start_edge + 100; // make pulse width = 1ns
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end
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else
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begin
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start_edge <= start_edge;
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end_edge <= end_edge;
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end
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end
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endmodule
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module vtest;
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wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9;
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wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17,
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vout18, vout19;
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reg clk, bit0;
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verr v0 (clk, vout0);
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verr v1 (clk, vout1);
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verr v2 (clk, vout2);
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verr v3 (clk, vout3);
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verr v4 (clk, vout4);
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verr v5 (clk, vout5);
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verr v6 (clk, vout6);
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verr v7 (clk, vout7);
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verr v8 (clk, vout8);
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verr v9 (clk, vout9);
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verr v10 (clk, vout10);
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verr v11 (clk, vout11);
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verr v12 (clk, vout12);
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verr v13 (clk, vout13);
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verr v14 (clk, vout14);
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verr v15 (clk, vout15);
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verr v16 (clk, vout16);
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verr v17 (clk, vout17);
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verr v18 (clk, vout18);
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verr v19 (clk, vout19);
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initial begin
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#10000 $display("This test doesn't check itself.");
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$display("PASSED");
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end
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endmodule
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