50 lines
762 B
Verilog
50 lines
762 B
Verilog
module tranif_or(a, b, y);
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input a, b;
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inout y;
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supply1 vdd;
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supply0 vss;
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wire w1, w2;
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// NOR
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tranif0(w1, vdd, a);
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tranif0(w2, w1, b);
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tranif1(w2, vss, a);
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tranif1(w2, vss, b);
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// OR
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tranif0(y, vdd, w2);
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tranif1(y, vss, w2);
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endmodule
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module test;
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reg a, b;
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wire y;
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tranif_or dut(a, b, y);
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reg failed = 0;
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initial begin
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$monitor("%t a=%b b=%b Y=%b", $time, a, b, y);
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#10 a = 0; b = 0;
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#0 if (y !== 0) failed = 1;
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#10 a = 0; b = 1;
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#0 if (y !== 1) failed = 1;
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#10 a = 1; b = 0;
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#0 if (y !== 1) failed = 1;
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#10 a = 1; b = 1;
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#0 if (y !== 1) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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