33 lines
393 B
Verilog
33 lines
393 B
Verilog
// Check that an ordinary port can match a visible interface name.
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interface I;
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endinterface
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module dut(
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input wire I,
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output wire value
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);
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assign value = I;
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endmodule
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module test;
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wire value;
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dut i_dut(.I(1'b1), .value(value));
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initial begin
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#1;
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if (value !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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