514 lines
13 KiB
C
514 lines
13 KiB
C
/*
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* Copyright (c) 2001-2014 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "device.h"
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# include "fpga_priv.h"
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# include <assert.h>
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/*
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* This is the device emitter for the most generic FPGA. It doesn't
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* know anything special about device types, so can't handle complex
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* logic.
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*/
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static void xnf_draw_pin(ivl_nexus_t nex, const char*nam, char dir)
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{
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const char*use_name = nam;
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const char*nex_name = xnf_mangle_nexus_name(nex);
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int invert = 0;
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if (use_name[0] == '~') {
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invert = 1;
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use_name += 1;
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}
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fprintf(xnf, " PIN, %s, %c, %s", use_name, dir, nex_name);
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if (invert)
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fprintf(xnf, ",,INV");
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fprintf(xnf, "\n");
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}
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static void show_root_ports_xnf(ivl_scope_t root)
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{
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unsigned cnt = ivl_scope_sigs(root);
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unsigned idx;
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for (idx = 0 ; idx < cnt ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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const char*use_name;
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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use_name = ivl_signal_basename(sig);
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if (ivl_signal_pins(sig) == 1) {
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ivl_nexus_t nex = ivl_signal_pin(sig, 0);
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fprintf(xnf, "SIG, %s, PIN=%s\n",
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xnf_mangle_nexus_name(nex), use_name);
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} else {
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unsigned pin;
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for (pin = 0 ; pin < ivl_signal_pins(sig); pin += 1) {
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ivl_nexus_t nex = ivl_signal_pin(sig, pin);
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fprintf(xnf, "SIG, %s, PIN=%s%u\n",
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xnf_mangle_nexus_name(nex), use_name,
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pin);
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}
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}
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}
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}
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static void show_design_consts_xnf(ivl_design_t des)
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{
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unsigned idx;
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for (idx = 0 ; idx < ivl_design_consts(des) ; idx += 1) {
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unsigned pin;
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ivl_net_const_t net = ivl_design_const(des, idx);
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const char*val = ivl_const_bits(net);
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for (pin = 0 ; pin < ivl_const_pins(net) ; pin += 1) {
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ivl_nexus_t nex = ivl_const_pin(net, pin);
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fprintf(xnf, "PWR,%c,%s\n", val[pin],
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xnf_mangle_nexus_name(nex));
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}
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}
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}
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static void generic_show_header(ivl_design_t des)
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{
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ivl_scope_t root = ivl_design_root(des);
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fprintf(xnf, "LCANET,6\n");
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fprintf(xnf, "PROG,iverilog,$Name: $,\"Icarus Verilog/fpga.tgt\"\n");
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if (part && (part[0]!=0)) {
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fprintf(xnf, "PART,%s\n", part);
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}
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show_root_ports_xnf(root);
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}
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static void generic_show_footer(ivl_design_t des)
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{
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show_design_consts_xnf(des);
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fprintf(xnf, "EOF\n");
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}
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static void generic_show_logic(ivl_net_logic_t net)
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{
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char name[1024];
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ivl_nexus_t nex;
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unsigned idx;
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xnf_mangle_logic_name(net, name, sizeof name);
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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fprintf(xnf, "SYM, %s, AND, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char ipin[32];
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nex = ivl_logic_pin(net, idx);
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sprintf(ipin, "I%u", idx-1);
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xnf_draw_pin(nex, ipin, 'I');
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}
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_BUF:
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assert(ivl_logic_pins(net) == 2);
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fprintf(xnf, "SYM, %s, BUF, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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nex = ivl_logic_pin(net, 1);
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xnf_draw_pin(nex, "I", 'I');
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_NAND:
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fprintf(xnf, "SYM, %s, NAND, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char ipin[32];
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nex = ivl_logic_pin(net, idx);
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sprintf(ipin, "I%u", idx-1);
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xnf_draw_pin(nex, ipin, 'I');
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}
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_NOR:
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fprintf(xnf, "SYM, %s, NOR, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char ipin[32];
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nex = ivl_logic_pin(net, idx);
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sprintf(ipin, "I%u", idx-1);
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xnf_draw_pin(nex, ipin, 'I');
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}
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_NOT:
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assert(ivl_logic_pins(net) == 2);
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fprintf(xnf, "SYM, %s, INV, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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nex = ivl_logic_pin(net, 1);
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xnf_draw_pin(nex, "I", 'I');
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_OR:
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fprintf(xnf, "SYM, %s, OR, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char ipin[32];
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nex = ivl_logic_pin(net, idx);
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sprintf(ipin, "I%u", idx-1);
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xnf_draw_pin(nex, ipin, 'I');
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}
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_XOR:
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fprintf(xnf, "SYM, %s, XOR, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char ipin[32];
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nex = ivl_logic_pin(net, idx);
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sprintf(ipin, "I%u", idx-1);
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xnf_draw_pin(nex, ipin, 'I');
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}
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_XNOR:
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fprintf(xnf, "SYM, %s, XNOR, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char ipin[32];
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nex = ivl_logic_pin(net, idx);
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sprintf(ipin, "I%u", idx-1);
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xnf_draw_pin(nex, ipin, 'I');
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}
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_BUFIF0:
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fprintf(xnf, "SYM, %s, TBUF, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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nex = ivl_logic_pin(net, 1);
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xnf_draw_pin(nex, "I", 'I');
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nex = ivl_logic_pin(net, 2);
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xnf_draw_pin(nex, "~T", 'I');
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fprintf(xnf, "END\n");
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break;
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case IVL_LO_BUFIF1:
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fprintf(xnf, "SYM, %s, TBUF, LIBVER=2.0.0\n", name);
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nex = ivl_logic_pin(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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nex = ivl_logic_pin(net, 1);
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xnf_draw_pin(nex, "I", 'I');
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nex = ivl_logic_pin(net, 2);
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xnf_draw_pin(nex, "T", 'I');
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fprintf(xnf, "END\n");
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break;
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default:
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fprintf(stderr, "fpga.tgt: unknown logic type %d\n",
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ivl_logic_type(net));
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break;
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}
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}
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static void generic_show_dff(ivl_lpm_t net)
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{
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char name[1024];
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ivl_nexus_t nex;
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xnf_mangle_lpm_name(net, name, sizeof name);
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fprintf(xnf, "SYM, %s, DFF, LIBVER=2.0.0\n", name);
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nex = ivl_lpm_q(net, 0);
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xnf_draw_pin(nex, "Q", 'O');
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nex = ivl_lpm_data(net, 0);
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xnf_draw_pin(nex, "D", 'I');
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nex = ivl_lpm_clk(net);
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xnf_draw_pin(nex, "C", 'I');
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if ((nex = ivl_lpm_enable(net)))
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xnf_draw_pin(nex, "CE", 'I');
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fprintf(xnf, "END\n");
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}
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/*
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* The generic == comparator uses EQN records to generate 2-bit
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* comparators, that are then connected together by a wide AND gate.
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*/
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static void generic_show_cmp_eq(ivl_lpm_t net)
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{
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ivl_nexus_t nex;
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unsigned idx;
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char name[1024];
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/* Make this many dual pair comparators, and */
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unsigned deqn = ivl_lpm_width(net) / 2;
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/* Make this many single pair comparators. */
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unsigned seqn = ivl_lpm_width(net) % 2;
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xnf_mangle_lpm_name(net, name, sizeof name);
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for (idx = 0 ; idx < deqn ; idx += 1) {
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fprintf(xnf, "SYM, %s/CD%u, EQN, "
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"EQN=(~((I0 @ I1) + (I2 @ I3)))\n",
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name, idx);
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fprintf(xnf, " PIN, O, O, %s/CDO%u\n", name, idx);
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nex = ivl_lpm_data(net, 2*idx);
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xnf_draw_pin(nex, "I0", 'I');
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nex = ivl_lpm_datab(net, 2*idx);
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xnf_draw_pin(nex, "I1", 'I');
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nex = ivl_lpm_data(net, 2*idx+1);
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xnf_draw_pin(nex, "I2", 'I');
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nex = ivl_lpm_datab(net, 2*idx+1);
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xnf_draw_pin(nex, "I3", 'I');
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fprintf(xnf, "END\n");
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}
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if (seqn != 0) {
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fprintf(xnf, "SYM, %s/CT, XNOR, LIBVER=2.0.0\n", name);
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fprintf(xnf, " PIN, O, O, %s/CTO\n", name);
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nex = ivl_lpm_data(net, 2*deqn);
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xnf_draw_pin(nex, "I0", 'I');
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nex = ivl_lpm_datab(net, 2*deqn);
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xnf_draw_pin(nex, "I1", 'I');
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fprintf(xnf, "END\n");
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}
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if (ivl_lpm_type(net) == IVL_LPM_CMP_EQ)
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fprintf(xnf, "SYM, %s/OUT, AND, LIBVER=2.0.0\n", name);
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else
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fprintf(xnf, "SYM, %s/OUT, NAND, LIBVER=2.0.0\n", name);
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nex = ivl_lpm_q(net, 0);
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xnf_draw_pin(nex, "O", 'O');
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for (idx = 0 ; idx < deqn ; idx += 1)
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fprintf(xnf, " PIN, I%u, I, %s/CDO%u\n", idx, name, idx);
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for (idx = 0 ; idx < seqn ; idx += 1)
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fprintf(xnf, " PIN, I%u, I, %s/CTO\n", deqn+idx, name);
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fprintf(xnf, "END\n");
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}
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/*
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* This function draws N-bit wide binary mux devices. These are so
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* very popular because they are the result of such expressions as:
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*
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* x = sel? a : b;
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*
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* This code only supports the case where sel is a single bit. It
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* works by drawing for each bit of the width an EQN device that takes
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* as inputs I0 and I1 the alternative inputs, and I2 the select. The
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* select bit is common with all the generated mux devices.
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*/
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static void generic_show_mux(ivl_lpm_t net)
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{
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char name[1024];
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ivl_nexus_t sel;
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unsigned idx;
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xnf_mangle_lpm_name(net, name, sizeof name);
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/* Access the single select bit. This is common to the whole
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width of the mux. */
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assert(ivl_lpm_selects(net) == 1);
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sel = ivl_lpm_select(net, 0);
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for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
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ivl_nexus_t nex;
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fprintf(xnf, "SYM, %s/M%u, EQN, "
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"EQN=((I0 * ~I2) + (I1 * I2))\n",
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name, idx);
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nex = ivl_lpm_q(net, idx);
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xnf_draw_pin(nex, "O", 'O');
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nex = ivl_lpm_data2(net, 0, idx);
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xnf_draw_pin(nex, "I0", 'I');
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nex = ivl_lpm_data2(net, 1, idx);
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xnf_draw_pin(nex, "I1", 'I');
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xnf_draw_pin(sel, "I2", 'I');
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fprintf(xnf, "END\n");
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}
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}
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/*
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* This code cheats and just generates ADD4 devices enough to support
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* the add. Make no effort to optimize, because we have no idea what
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* kind of device we have.
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*/
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static void generic_show_add(ivl_lpm_t net)
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{
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char name[1024];
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ivl_nexus_t nex;
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unsigned idx, nadd4, tail;
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xnf_mangle_lpm_name(net, name, sizeof name);
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/* Make this many ADD4 devices. */
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nadd4 = ivl_lpm_width(net) / 4;
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tail = ivl_lpm_width(net) % 4;
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for (idx = 0 ; idx < nadd4 ; idx += 1) {
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fprintf(xnf, "SYM, %s/A%u, ADD4\n", name, idx);
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if (idx > 0)
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fprintf(xnf, " PIN, CI, I, %s/CO%u\n", name, idx-1);
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nex = ivl_lpm_q(net, idx*4+0);
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xnf_draw_pin(nex, "S0", 'O');
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nex = ivl_lpm_q(net, idx*4+1);
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xnf_draw_pin(nex, "S1", 'O');
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nex = ivl_lpm_q(net, idx*4+2);
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xnf_draw_pin(nex, "S2", 'O');
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nex = ivl_lpm_q(net, idx*4+3);
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xnf_draw_pin(nex, "S3", 'O');
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nex = ivl_lpm_data(net, idx*4+0);
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xnf_draw_pin(nex, "A0", 'I');
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nex = ivl_lpm_data(net, idx*4+1);
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xnf_draw_pin(nex, "A1", 'I');
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nex = ivl_lpm_data(net, idx*4+2);
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xnf_draw_pin(nex, "A2", 'I');
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nex = ivl_lpm_data(net, idx*4+3);
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xnf_draw_pin(nex, "A3", 'I');
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nex = ivl_lpm_datab(net, idx*4+0);
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xnf_draw_pin(nex, "B0", 'I');
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nex = ivl_lpm_datab(net, idx*4+1);
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xnf_draw_pin(nex, "B1", 'I');
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nex = ivl_lpm_datab(net, idx*4+2);
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xnf_draw_pin(nex, "B2", 'I');
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nex = ivl_lpm_datab(net, idx*4+3);
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xnf_draw_pin(nex, "B3", 'I');
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if ((idx*4+4) < ivl_lpm_width(net))
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fprintf(xnf, " PIN, CO, O, %s/CO%u\n", name, idx);
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fprintf(xnf, "END\n");
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}
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if (tail > 0) {
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fprintf(xnf, "SYM, %s/A%u, ADD4\n", name, nadd4);
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if (nadd4 > 0)
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fprintf(xnf, " PIN, CI, I, %s/CO%u\n", name, nadd4-1);
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switch (tail) {
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case 3:
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nex = ivl_lpm_data(net, nadd4*4+2);
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|
xnf_draw_pin(nex, "A2", 'I');
|
|
|
|
nex = ivl_lpm_datab(net, nadd4*4+2);
|
|
xnf_draw_pin(nex, "B2", 'I');
|
|
|
|
nex = ivl_lpm_q(net, nadd4*4+2);
|
|
xnf_draw_pin(nex, "S2", 'O');
|
|
case 2:
|
|
nex = ivl_lpm_data(net, nadd4*4+1);
|
|
xnf_draw_pin(nex, "A1", 'I');
|
|
|
|
nex = ivl_lpm_datab(net, nadd4*4+1);
|
|
xnf_draw_pin(nex, "B1", 'I');
|
|
|
|
nex = ivl_lpm_q(net, nadd4*4+1);
|
|
xnf_draw_pin(nex, "S1", 'O');
|
|
case 1:
|
|
nex = ivl_lpm_data(net, nadd4*4+0);
|
|
xnf_draw_pin(nex, "A0", 'I');
|
|
|
|
nex = ivl_lpm_datab(net, nadd4*4+0);
|
|
xnf_draw_pin(nex, "B0", 'I');
|
|
|
|
nex = ivl_lpm_q(net, nadd4*4+0);
|
|
xnf_draw_pin(nex, "S0", 'O');
|
|
}
|
|
|
|
fprintf(xnf, "END\n");
|
|
}
|
|
}
|
|
|
|
const struct device_s d_generic = {
|
|
generic_show_header,
|
|
generic_show_footer,
|
|
0, /* show_scope */
|
|
0, /* show_pad not implemented */
|
|
generic_show_logic,
|
|
generic_show_dff,
|
|
generic_show_cmp_eq,
|
|
generic_show_cmp_eq,
|
|
0, /* ge not implemented */
|
|
0, /* gt not implemented */
|
|
generic_show_mux,
|
|
generic_show_add,
|
|
0, /* subtract not implemented */
|
|
0,
|
|
0
|
|
};
|