45 lines
1.4 KiB
Plaintext
45 lines
1.4 KiB
Plaintext
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BLIF TARGET
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-----------
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The BLIF code generator supports emitting the design to a blif format
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file as accepted by:
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ABC: A System for Sequential Synthesis and Verification
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<http://www.eecs.berkeley.edu/~alanmi/abc/>
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This package contains tools sometimes used by ASIC designers. This
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blif target emits .blif file that the ABC system can read int via
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the "read_blif" command.
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USAGE
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-----
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This code generator is intended to process structural Verilog source
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code. To convert a design to blif, use this command:
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iverilog -tblif -o<path>.blif <source files>...
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The source files can be Verilog, SystemVerilog, VHDL, whatever Icarus
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Verilog supports, so long as it elaborates down to the limited subset
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that the code generator supports. In other words, the files must be
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structural.
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The root module of the elaborated design becomes the model is
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generated. That module may instantiate sub-modules and so on down the
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design, completing the design. The output model is flattened, so it
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doesn't invoke any subcircuits. Bit vectors are exploded out at the
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model ports and internally. This is necessary since blif in particular
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and ABC in general processes bits, not vectors.
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LIMITATIONS
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-----------
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Currently, only explicit logic gates and continuous assignments are
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supported.
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The design must contain only one root module. The name of that root
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module becomes the name of the blif model in the ".model" record.
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