104 lines
3.7 KiB
Plaintext
104 lines
3.7 KiB
Plaintext
/*
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* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/*
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* This example demonstrates Icarus Verilog's ability to synthesize
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* efficient adders for Xilinx 4000 series FPGAs. The synthesis and
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* code generation makes an adder and translates that into XOR gates
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* and fast carry chain hardware.
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*
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* To compile this for XNF, try a command like this:
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*
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* iverilog -txnf -ppart=XC4010XLPQ160 -pncf=xnf_add.ncf -oxnf_add.xnf xnf_add.v
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*
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* That command causes an xnf_add.xnf and xnf_add.ncf file to be created.
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* Next, Use Xilinx Alliance or Foundation tools to make the xnf_add.ngd
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* file with the command:
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*
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* xnf2ngd -l xilinxun -u xnf_add.xnf xnf_add.ngo
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* ngdbuild xnf_add.ngo xnf_add.ngd
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*
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* Finally, map the file to fully render it in the target part. The
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* par command is the step that actually optimizes the design and tries
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* to meet timing constraints.
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*
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* map -o map.ncd xnf_add.ngd
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* par -w map.ncd xnf_add.ncd
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*
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* At this point, you can use the Xilinx FPGA Editor to edit the xnf_add.ncd
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* file and see the carry chains made up to support the adder.
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*/
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module main;
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wire [3:0] a, b;
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wire [3:0] out;
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wire carry;
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wire a0, a1, a2, a3, b0, b1, b2, b3;
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wire out0, out1, out2, out3;
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// This creates the actual adder. Note that we also create a link
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// to the carry output. The principle adder is 4 bits wide, so two
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// IOBs are used to to the actual addition. PAR will place them in
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// order along carry lines. An extra carry cell from below a[0] is
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// used in FORCE-0 mode to load the bottom carry node.
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//
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// The carry signal from the top CY device is used to drive the
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// main.carry wire shown here. It is managed in this case by using
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// an ADD-FG-CI CY device for the top pair and using the CLB above
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// the carry chain, with its CY in EXAMINE-CI mode, to put the carry
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// out through its G function unit.
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assign {carry, out} = a + b;
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// These attribute commands assign pins to the listed wires.
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// This can be done to wires and registers, as internally both
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// are treated as named signals. It doesn't work (yet) on vectors,
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// though, so break out the vectors with scalar assignments.
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assign a[0] = a0;
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assign a[1] = a1;
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assign a[2] = a2;
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assign a[3] = a3;
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$attribute(a0, "PAD", "i150");
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$attribute(a1, "PAD", "i152");
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$attribute(a2, "PAD", "i153");
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$attribute(a3, "PAD", "i154");
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assign b[0] = b0;
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assign b[1] = b1;
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assign b[2] = b2;
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assign b[3] = b3;
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$attribute(b0, "PAD", "i155");
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$attribute(b1, "PAD", "i156");
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$attribute(b2, "PAD", "i157");
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$attribute(b3, "PAD", "i158");
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assign out0 = out[0];
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assign out1 = out[1];
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assign out2 = out[2];
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assign out3 = out[3];
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$attribute(out0, "PAD", "o71");
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$attribute(out1, "PAD", "o72");
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$attribute(out2, "PAD", "o73");
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$attribute(out3, "PAD", "o74");
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$attribute(carry, "PAD", "o75");
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endmodule /* main */
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