Files
iverilog/tgt-vvp
Stephen Williams a2dc1e0a29 Add means for &A<> to index using a calculated index.
This is not a solution to all the problems, but is a better catch-all
then what is currently there. Allow the index field to be a T<> that
accesses the thread to get the address index.

Note that the lexor.lex currently returns the T<> as a T_SYMBOL, and the
users of T_SYMBOL objects need to interpret the meaning. This is
probably not the best idea, in light of all the other *<> formats that
now exist.
2008-06-08 21:38:35 -07:00
..
2005-03-18 02:57:23 +00:00
2008-05-19 17:37:23 -07:00
2008-05-29 14:00:32 -07:00
2008-05-22 20:24:21 -07:00
2008-04-15 21:51:03 -07:00
2008-04-15 21:51:03 -07:00

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.


GENERAL FUNCTOR WEB STRUCTURE

The net of gates, signals and resolvers is formed from the input
design. The basic structure is wrapped around the nexus, which is
represented by the ivl_nexus_t.

Each nexus represents a resolved value. The input of the nexus is fed
by a single driver. If the nexus in the design has multiple drivers,
the drivers are first fed into a resolver (or a tree of resolvers) to
form a single output that is the nexus.

The nexus, then, feeds its output to the inputs of other gates, or to
the .net objects in the design.