31 lines
740 B
Verilog
31 lines
740 B
Verilog
// Phase 0 test design: a counter instantiated inside a top module,
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// to exercise scope hierarchy + nexus reachability in tgt-flow.
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module counter #(parameter WIDTH = 4) (
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input wire clk,
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input wire rst,
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input wire en,
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output reg [WIDTH-1:0] count
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);
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always @(posedge clk or posedge rst) begin
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if (rst)
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count <= {WIDTH{1'b0}};
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else if (en)
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count <= count + 1'b1;
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end
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endmodule
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module top (
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input wire clk,
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input wire rst,
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output wire [3:0] q
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);
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wire enable = 1'b1;
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counter #(.WIDTH(4)) u_cnt (
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.clk (clk),
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.rst (rst),
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.en (enable),
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.count (q)
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);
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endmodule
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