41 lines
706 B
Verilog
41 lines
706 B
Verilog
// Check that static lifetime can be specified for variables declared in a
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// package.
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end
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package P;
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static int x = 1;
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const static int y = 2;
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var static z;
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var static logic [3:0] w = 4'h3;
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endpackage
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package automatic Q;
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int a = 4;
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static int b = 5;
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endpackage
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module test;
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import P::*;
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import Q::*;
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bit failed = 1'b0;
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initial begin
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`check(x, 1)
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`check(y, 2)
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`check(z, 1'bx)
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`check(w, 4'h3)
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`check(a, 4)
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`check(b, 5)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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