42 lines
918 B
VHDL
42 lines
918 B
VHDL
--
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-- Support routines for Icarus Verilog VHDL output
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package Verilog_Support is
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-- This routine implements $finish by terminating the simulation
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-- It is implemented via the VHPI interface
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procedure finish;
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attribute foreign of finish : procedure is "VHPIDIRECT finish";
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-- Routines to implement Verilog reduction operators
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function Reduce_OR(X : unsigned) return std_logic;
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end Verilog_Support;
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package body Verilog_Support is
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-- This is a dummy body to provide a default implementation
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-- if VHPI is not supported
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procedure finish is
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begin
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assert false severity failure;
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end finish;
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function Reduce_OR(X : unsigned) return std_logic is
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begin
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for I in X'range loop
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if X(I) /= '1' then
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return '0';
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end if;
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end loop;
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return '1';
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end function;
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end Verilog_Support;
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