Files
iverilog/vpi
Martin Whitaker 7bed181f68 Support timescales in design units that aren't inside a module.
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
..
2015-12-19 11:58:31 -08:00
2016-03-24 20:23:47 -07:00
2014-07-08 14:14:39 -07:00
2015-10-02 10:32:34 -07:00
2015-10-02 10:32:34 -07:00
2013-04-15 11:54:15 -07:00
2014-07-08 13:44:11 -07:00
2014-04-27 17:57:43 -07:00
2012-08-29 10:12:10 -07:00
2014-07-09 14:16:57 -07:00
2015-07-22 09:53:42 -07:00
2014-07-08 13:44:11 -07:00
2015-02-25 17:52:44 -08:00
2015-10-31 11:17:18 +01:00
2014-07-08 13:44:11 -07:00
2014-07-08 13:44:11 -07:00
2014-07-08 13:44:11 -07:00
2014-07-09 14:16:57 -07:00
2016-01-06 15:30:06 +01:00
2015-07-22 10:02:33 -07:00
2014-07-09 14:16:57 -07:00
2014-07-08 13:44:11 -07:00
2014-07-09 14:16:57 -07:00