75 lines
1.6 KiB
Verilog
75 lines
1.6 KiB
Verilog
module xortest(out, a, b);
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output out;
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input a, b;
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parameter tdelay=2;
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wire a_, b_, i1, i2, i3;
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supply0 gnd;
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supply1 vdd;
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nmos #(tdelay) n5(a_, gnd, a);
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pmos #(tdelay) p5(a_, vdd, a);
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nmos #(tdelay) n6(b_, gnd, b);
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pmos #(tdelay) p6(b_, vdd, b);
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nmos #(tdelay) n1(out, i1, a);
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nmos #(tdelay) n2(i1, gnd, b);
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nmos #(tdelay) n3(out, i2, a_);
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nmos #(tdelay) n4(i2, gnd, b_);
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pmos #(tdelay) p1(out, i3, a);
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pmos #(tdelay) p2(out, i3, b);
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pmos #(tdelay) p3(i3, vdd, a_);
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pmos #(tdelay) p4(i3, vdd, b_);
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endmodule
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module testXor();
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wire out;
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reg a, b;
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reg pass;
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xortest x1(out, a, b);
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initial begin
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pass = 1'b1;
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a=1;b=1;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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a=0;b=1;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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a=1;b=0;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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a=0;b=0;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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repeat (3) begin
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a=0;b=1;
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#100; $display("REP A=%b B=%b Out=%b",a,b,out);
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a=1;b=0;
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#100; $display("REP A=%b B=%b Out=%b",a,b,out);
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end
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a=1;b=1;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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a=0;b=1;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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a=1;b=0;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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a=0;b=0;
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#100; $display("A=%b B=%b Out=%b",a,b,out);
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if (pass) $display("PASSED");
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end
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always @(out) begin
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// Wait for the value to settle.
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#10 if (out !== (a ^ b)) begin
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$display("Failed at %0t, expected %b, got %b, with a=%b, b=%b",
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$time, a ^ b, out, a, b);
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pass = 1'b0;
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end
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end
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endmodule
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