38 lines
513 B
Verilog
38 lines
513 B
Verilog
`timescale 1ns/1ps
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module Buffer(output Y, input A);
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specparam Delay = 0.1;
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assign #Delay Y = A;
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endmodule
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module Buffer1(output Y, input A);
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Buffer inst(.Y(Y), .A(A));
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endmodule
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module Buffer2(output Y, input A);
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Buffer inst(.Y(Y), .A(A));
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endmodule
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`timescale 1ps/1ps
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module dut();
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reg n1;
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wire n2;
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wire n3;
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Buffer1 b1(.A(n1), .Y(n2));
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Buffer2 b2(.A(n2), .Y(n3));
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initial begin
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$monitor("%t %b %b %b", $time, n1, n2, n3);
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#1000 n1 = 0;
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#1000 n1 = 1;
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#1000 $finish(0);
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end
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endmodule
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