41 lines
786 B
Verilog
41 lines
786 B
Verilog
module test;
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localparam NOM_COUNT = 1000;
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localparam MIN_COUNT = NOM_COUNT - 200;
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localparam MAX_COUNT = NOM_COUNT + 200;
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integer histogram[255:0];
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integer i;
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reg [7:0] value;
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reg failed;
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initial begin
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failed = 0;
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for (i = 0; i < 256; i++) begin
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histogram[i] = 0;
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end
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for (i = 0; i < 256*NOM_COUNT; i = i + 1) begin
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value = $urandom_range(32'hffffffff, 32'h0) >> 24;
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histogram[value] += 1;
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end
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for (i = 0; i < 256; i++) begin
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if (histogram[i] < MIN_COUNT) begin
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$display("Bin %3d count %0d", i, histogram[i]);
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failed = 1;
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end
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if (histogram[i] > MAX_COUNT) begin
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$display("Bin %3d count %0d", i, histogram[i]);
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failed = 1;
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end
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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