41 lines
1006 B
Verilog
41 lines
1006 B
Verilog
module top;
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// Test the shortreal conversion functions, but we don't support shortreal
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// as a type yet so be safe with the actual values that are checked to
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// avoid any real (double) to shortreal (float) rounding.
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real in;
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reg [31:0] irep;
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real res;
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reg passed;
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initial begin
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passed = 1'b1;
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in = 0.0;
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irep = $shortrealtobits(in);
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res = $bitstoshortreal(irep);
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if (in != res) begin
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$display("Input and output value do not match (%f != %f)", in, res);
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passed = 1'b0;
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end
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in = 8.0;
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irep = $shortrealtobits(in);
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res = $bitstoshortreal(irep);
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if (in != res) begin
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$display("Input and output value do not match (%f != %f)", in, res);
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passed = 1'b0;
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end
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in = 0.125;
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irep = $shortrealtobits(in);
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res = $bitstoshortreal(irep);
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if (in != res) begin
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$display("Input and output value do not match (%f != %f)", in, res);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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