91 lines
3.2 KiB
ReStructuredText
91 lines
3.2 KiB
ReStructuredText
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Icarus Verilog Extensions
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=========================
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Icarus Verilog supports certain extensions to the baseline IEEE 1364
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standard. Some of these are picked from extended variants of the
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language, such as SystemVerilog, and some are expressions of internal
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behavior of Icarus Verilog, made available as a tool debugging aid.
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Built-in System Functions
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-------------------------
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Extended Verilog Data Types
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---------------------------
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This feature is turned on by the generation flag "-gxtypes" and turned
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off by the generation flag "-gno-xtypes". It is turned on by default.
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Icarus Verilog adds support for extended data types. This extended
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type syntax is based on a proposal by Cadence Design Systems,
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originally as an update to the IEEE 1364 standard. Icarus Verilog
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currently only takes the new primitive types from the proposal.
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SystemVerilog provides the same functionality using somewhat different
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syntax. This extension is maintained for backwards compatibility.
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- Types
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Extended data types separates the concept of net/variable from the
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data type. Both nets and variables can declared with any data
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type. The primitive types available are::
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logic - The familiar 0, 1, x and z, optionally with strength.
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bool - Limited to only 0 and 1
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real - 64-bit real values
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Nets with logic type may have multiple drivers with strength, and the
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value is resolved the usual way. Only logic values may be driven to
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logic nets, so bool values driven onto logic nets are implicitly
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converted to logic.
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Nets with any other type may not have multiple drivers. The compiler
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should detect the multiple drivers and report an error.
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- Declarations
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The declaration of a net is extended to include the type of the wire,
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with the syntax::
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wire <type> <wire-assignment-list>... ;
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The <type>, if omitted, is taken to be logic. The "wire" can be any of
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the net keywords. Wires can be logic, bool, real, or vectors of logic
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or bool. Some valid examples::
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wire real foo = 1.0;
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tri logic bus[31:0];
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wire bool addr[23:0];
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... and so on.
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The declarations of variables is similar. The "reg" keyword is used to
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specify that this is a variable. Variables can have the same data
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types as nets.
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- Ports
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Module and task ports in standard Verilog are restricted to logic
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types. This extension removes that restriction, allowing any of
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the above types to pass through the port consistent with the
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continuous assignment connectivity that is implied by the type.
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- Expressions
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Expressions in the face of real values is covered by the baseline
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Verilog standard.
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The bool type supports the same operators as the logic type, with the
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obvious differences imposed by the limited domain.
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Comparison operators (not case compare) return logic if either of
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their operands is logic. If both are bool or real (including mix of
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bool and real) then the result is bool. This is because comparison of
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bools and reals always return exactly true or false.
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Case comparison returns bool. This differs from baseline Verilog,
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which strictly speaking returns a logic, but only 0 or 1 values.
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Arithmetic operators return real if either of their operands is real,
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otherwise they return logic if either of their operands is logic. If
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both operands are bool, they return bool.
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