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Stephen Williams
6c9c876c83
This includes support at the parser (pform) through enaboration and the netlist format for the break and continue statements. Elaboration actually already worked for for-loops, but since the code generators need more information, this is a rewire of that support to be explicit about for-loops. This means they are not rewritten as fancy while loops. The code generators will have to handle that. Given the elaboration of for-loops now work, write the vvp code generator support needed to implement it. Now that for-loops are presented as for-loops to the code generator, the vlog95 code generator doesn't need to infer them anymore. Generate the code more directly. Also update the tests list so that the vlog95_reg tests all pass.
THE VVP TARGET SYMBOL NAME CONVENTIONS There are some naming conventions that the vvp target uses for generating symbol names. * wires and regs Nets and variables are named V_<full-name> where <full-name> is the full hierarchical name of the signal. * Logic devices Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In this case the symbol is attached to a functor that is the output of the logic device. GENERAL FUNCTOR WEB STRUCTURE The net of gates, signals and resolvers is formed from the input design. The basic structure is wrapped around the nexus, which is represented by the ivl_nexus_t. Each nexus represents a resolved value. The input of the nexus is fed by a single driver. If the nexus in the design has multiple drivers, the drivers are first fed into a resolver (or a tree of resolvers) to form a single output that is the nexus. The nexus, then, feeds its output to the inputs of other gates, or to the .net objects in the design.