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iverilog/vhdlpp
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Stephen Williams 791adfab68 Check ports match up in component instantiations. 
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
 		2011-04-10 09:42:22 -07:00
..
Makefile.in Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
README.txt Create an Architecture class and bind them to their entities. 2011-02-13 16:43:04 -08:00
architec.cc Check ports match up in component instantiations. 2011-04-10 09:42:22 -07:00
architec.h Check ports match up in component instantiations. 2011-04-10 09:42:22 -07:00
architec_elaborate.cc Check ports match up in component instantiations. 2011-04-10 09:42:22 -07:00
architec_emit.cc Basic elaboration of vhdl component instantiations. 2011-03-31 19:07:43 -07:00
compiler.cc Add file/line information to entities and ports 2011-01-18 17:03:51 -08:00
compiler.h Add file/line information to entities and ports 2011-01-18 17:03:51 -08:00
debug.cc Basic elaboration of vhdl component instantiations. 2011-03-31 19:07:43 -07:00
entity.cc Check ports match up in component instantiations. 2011-04-10 09:42:22 -07:00
entity.h Check ports match up in component instantiations. 2011-04-10 09:42:22 -07:00
entity_elaborate.cc Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
entity_emit.cc Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
expression.cc Add use clause parsing 2011-03-31 18:57:25 -07:00
expression.h Add use clause parsing 2011-03-31 18:57:25 -07:00
expression_emit.cc Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
lexor.lex Merge branch 'master' into work4 2011-03-14 17:34:57 -07:00
lexor_keyword.gperf Fix remaining space issues. 2011-03-14 16:26:31 -07:00
main.cc Parse component declarations / parse signal declarations. 2011-03-22 09:18:20 -07:00
parse.y Check ports match up in component instantiations. 2011-04-10 09:42:22 -07:00
parse_api.h Spelling fixes 2011-03-29 08:56:10 -07:00
parse_misc.cc Soft treating of multiple architectures in VHDL 2011-03-23 11:45:33 -07:00
parse_misc.h Stub support for "use" directives. 2011-02-19 13:08:26 -08:00
parse_types.h Add basic instantiation list handling in VHDL 2011-04-02 09:27:58 -07:00
parse_wrap.h Basic elaboration of vhdl component instantiations. 2011-03-31 19:07:43 -07:00
vhdlint.cc Merge branch 'master' into work4 2011-03-14 17:34:57 -07:00
vhdlint.h Fix spacing problems. 2011-03-03 11:21:31 -08:00
vhdlnum.h Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
vhdlpp_config.h.in
…
vhdlreal.cc Fix spacing problems. 2011-03-03 11:21:31 -08:00
vhdlreal.h Fix spacing problems. 2011-03-03 11:21:31 -08:00
vsignal.cc Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
vsignal.h Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
vtype.cc Handle signed stdlogic. 2011-02-27 10:33:37 -08:00
vtype.h Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
vtype_elaborate.cc Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00
vtype_emit.cc Add more complete support for vhdl local signals. 2011-03-28 14:34:02 -07:00

README.txt 

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be

  * yydebug | no-yydebug

  * entities=<path>

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.