20 lines
466 B
Verilog
20 lines
466 B
Verilog
// Check that positional assigment patterns are supported for packed arrays.
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module test;
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bit [3:0][3:0] x = '{1'b1, 1 + 1, 3.0, "TEST"};
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// Check nested assignment pattern
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bit [1:0][3:0][3:0] y = '{'{1'b1, 1 + 1, 3.0, "TEST"},
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'{5, 6, '{1'b0, 1 * 1, 3, 1.0}, 8}};
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initial begin
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if (x === 16'h1234 && y == 32'h12345678) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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