40 lines
759 B
Verilog
40 lines
759 B
Verilog
module main;
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parameter [15:0] a = 16'h8421;
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reg [3:0] b, c;
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reg pass;
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always @* begin
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b = a[c+:4];
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// $display($time, " c: %d, b: %h", c, b);
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end
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initial begin
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pass = 1'b1;
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c = 0;
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#1 if (b !== 4'd1) begin
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$display("FAILED: c = 0, expected 1, got %0d", b);
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pass = 1'b0;
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end
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#9 c = 4;
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#1 if (b !== 4'd2) begin
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$display("FAILED: c = 4, expected 2, got %0d", b);
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pass = 1'b0;
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end
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#9 c = 8;
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#1 if (b !== 4'd4) begin
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$display("FAILED: c = 8, expected 4, got %0d", b);
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pass = 1'b0;
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end
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#9 c = 12;
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#1 if (b !== 4'd8) begin
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$display("FAILED: c = 12, expected 8, got %0d", b);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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