37 lines
670 B
Verilog
37 lines
670 B
Verilog
`timescale 1ns/10ps
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module top;
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// Comment out this line and the $display below to get elaboration to fail.
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integer max = 2 ** 2;
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initial begin
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test_ok;
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// test_fail;
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$display("Main: %3d", max);
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end
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// This works.
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task test_ok;
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integer max;
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begin
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max = 2 ** 8;
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$display("OK: %3d", max);
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end
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endtask
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/*
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* This is invalid syntax! You can not do an assignment in a block
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* level variable declaration (task, function, etc.).
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// And this is failing! It appears to be looking in the wrong scope.
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task test_fail;
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integer max = 2 ** 8;
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begin
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$display("Fail: %3d", max);
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end
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endtask
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*/
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endmodule
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