19 lines
362 B
Verilog
19 lines
362 B
Verilog
module Module;
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parameter T = 10;
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wire [T-1:0] x = 8'h55;
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initial $display("Module %b %0d", x, T);
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endmodule
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module top;
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wire [7:0] x;
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Module #($bits(x)) mA();
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Module #(8) mB();
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initial begin
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if (mA.x === 8'h55 && mB.x === 8'h55)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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