26 lines
403 B
Verilog
26 lines
403 B
Verilog
module top;
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wire x, y, z;
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reg in;
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genvar i;
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generate
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for (i=0; i<1; i=i+1) begin
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assign x = in;
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end
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generate // This should be an error
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for (i=0; i<1; i=i+1) begin
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assign y = in;
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end
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endgenerate
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endgenerate
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generate // This is ok
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for (i=0; i<1; i=i+1) begin
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assign z = in;
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end
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endgenerate
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initial $display("Failed: should be a compile error!");
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endmodule
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