25 lines
520 B
Verilog
25 lines
520 B
Verilog
module top;
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reg [3:0] inp1;
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reg signed [3:0] inp2;
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wire [4:0] out1, out2;
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initial begin
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$monitor("%b %b %b %b", inp1, inp2, out1, out2);
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#1 inp1 = 4'b1111;
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#1 inp2 = 4'b1111;
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#1;
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if ((out1 === 5'b01111) && (out2 === 5'b01111))
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$display("PASSED");
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else
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$display("FAILED");
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end
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mod m1({inp1}, out1);
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mod m2({inp2}, out2);
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endmodule
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module mod(
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input [4:0] inp,
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output [4:0] out
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);
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assign out = inp;
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endmodule
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