24 lines
513 B
Verilog
24 lines
513 B
Verilog
// Check whether it is possible to declare a parameter in a generate block
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// In Verilog this should fail, in SystemVerilog the parameter is elaborated as
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// localparam and the test should pass.
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module test;
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generate
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genvar i;
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for (i = 0; i < 2; i = i + 1) begin : loop
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parameter A = i;
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reg [A:0] r = A+1;
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end
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endgenerate
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initial begin
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if (loop[0].r == 1 && loop[1].r == 2) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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