31 lines
554 B
Verilog
31 lines
554 B
Verilog
// Check that single element static unpacked array elements can be used in
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// continuous l-value concatenations.
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module test;
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reg failed;
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wire [7:0] a[0:0];
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reg [7:0] y;
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assign {a[0]} = y;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %h, got %h", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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y = 8'h78;
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#1;
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`check(a[0], 8'h78);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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